[bknr-cvs] hans changed trunk/projects/rekonstrukt/src/testbench/

[BKNR Commits]

Revision: 4157
Author: hans
URL: http://bknr.net/trac/changeset/4157

Commit testbench sources

A   trunk/projects/rekonstrukt/src/testbench/
A   trunk/projects/rekonstrukt/src/testbench/rekonstrukt_clocks_TB.vhd
A   trunk/projects/rekonstrukt/src/testbench/rekonstrukt_clocks_TB_runtest.do

Added: trunk/projects/rekonstrukt/src/testbench/rekonstrukt_clocks_TB.vhd
===================================================================
--- trunk/projects/rekonstrukt/src/testbench/rekonstrukt_clocks_TB.vhd	                        (rev 0)
+++ trunk/projects/rekonstrukt/src/testbench/rekonstrukt_clocks_TB.vhd	2009-01-19 19:00:15 UTC (rev 4157)
@@ -0,0 +1,73 @@
+library ieee;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+library unisim;
+use unisim.vcomponents.all;
+
+-- Add your library and packages declaration here ...
+
+entity rekonstrukt_clocks_tb is
+end rekonstrukt_clocks_tb;
+
+architecture TB_ARCHITECTURE of rekonstrukt_clocks_tb is
+  -- Component declaration of the tested unit
+  component rekonstrukt_clocks
+    port(
+      sysclk : in STD_LOGIC;
+      bpm : in STD_LOGIC_VECTOR(6 downto 0);
+      reset : in STD_LOGIC;
+      clk_96ths : out STD_LOGIC;
+      clk_midi : out STD_LOGIC );
+  end component;
+
+  -- Stimulus signals - signals mapped to the input and inout ports of tested entity
+  signal sysclk : STD_LOGIC;
+  signal bpm : STD_LOGIC_VECTOR(6 downto 0);
+  signal reset : STD_LOGIC;
+  -- Observed signals - signals mapped to the output ports of tested entity
+  signal clk_96ths : STD_LOGIC;
+  signal clk_midi : STD_LOGIC;
+
+  -- Add your code here ...
+
+begin
+
+  -- Unit Under Test port map
+  UUT : rekonstrukt_clocks
+    port map (
+      sysclk => sysclk,
+      bpm => bpm,
+      reset => reset,
+      clk_96ths => clk_96ths,
+      clk_midi => clk_midi
+      );
+
+  -- Add your stimulus here ...
+  clock_stimulus : process
+  begin
+    sysclk <= '1';
+    wait for 31.25 ns;
+    sysclk <= '0';
+    wait for 31.25 ns;
+  end process;
+
+  reset_stimulus : process
+  begin
+    reset <= '1';
+    wait for 1 us;
+    reset <= '0';
+    wait;
+  end process;
+
+  bpm <= "0001000";
+
+end TB_ARCHITECTURE;
+
+configuration TESTBENCH_FOR_rekonstrukt_clocks of rekonstrukt_clocks_tb is
+  for TB_ARCHITECTURE
+    for UUT : rekonstrukt_clocks
+      use entity work.rekonstrukt_clocks(rekonstrukt_clocks_arch);
+    end for;
+  end for;
+end TESTBENCH_FOR_rekonstrukt_clocks;
+

Added: trunk/projects/rekonstrukt/src/testbench/rekonstrukt_clocks_TB_runtest.do
===================================================================
--- trunk/projects/rekonstrukt/src/testbench/rekonstrukt_clocks_TB_runtest.do	                        (rev 0)
+++ trunk/projects/rekonstrukt/src/testbench/rekonstrukt_clocks_TB_runtest.do	2009-01-19 19:00:15 UTC (rev 4157)
@@ -0,0 +1,14 @@
+SetActiveLib -work
+comp -include "$DSN\src\clkdiv.vhd" 
+comp -include "$DSN\src\clocks.vhd" 
+comp -include "$DSN\src\testbench\rekonstrukt_clocks_TB.vhd" 
+asim TESTBENCH_FOR_rekonstrukt_clocks 
+wave 
+wave -noreg sysclk
+wave -noreg bpm
+wave -noreg clk_96ths
+wave -noreg clk_midi
+# The following lines can be used for timing simulation
+# acom <backannotated_vhdl_file_name>
+# comp -include "$DSN\src\testbench\rekonstrukt_clocks_TB_tim_cfg.vhd" 
+# asim TIMING_FOR_rekonstrukt_clocks